Chemical Mechanical Polishing (CMP) is a process that is used for the planarization of semiconductor wafers. CMP takes advantages of the synergetic effect of both physical and chemical forces for polishing of wafers. It is done by applying a load force to the back of a wafer while it rests on a pad. Both the pad and wafer are then counter rotated while a slurry containing both abrasives and reactive chemicals is passed underneath. CMP is an effective way for achieving truly global planarization over the entire substrate.
The existence of pattern effect in films polished by CMP processes has been well known. A so-called “micro-loading effect” problem occurs due to a difference in pattern density and degrades the uniformity of pattern sizes. The “micro-loading effect” pertains to a phenomenon occurring upon simultaneously etching or polishing a region of a higher pattern density and a region of a lower pattern density: due to a difference in the etching/polishing rate of a film from one region to another, the amount of reaction produced by the etching/polishing process becomes locally dense or sparse, and convection of a large amount of reaction products causes an un-uniformity in etching rate. Large variations in effective pattern density have been shown to result in significant and undesirable post-polish film thickness variation. Particularly, this un-uniformity causes a “dishing” effect on the surface of the circuit. “Dishing” means that the surface at a location with lower pattern density was polished faster than the surface with higher pattern density, hence forming a dish shaped surface.
To counteract this effect, two methods are typically used to equalize the effective pattern density across the die. The first method is a process step known as reverse etch back, which involves using a mask to etch back raised areas. The second method is a layout design step known as dummy fill, where the circuit layout is modified and dummy patterns are added to locations with low pattern density. The adding of dummy patterns helps to achieve uniform effective pattern density across the wafer, therefore avoiding the dishing problem.
Conventionally, such dummy patterns are left in place after CMP. In the case where dummy patterns are conductive, they form parasitic capacitance with the interlayer metal wiring. The parasitic capacitance contributes to the RC time delay due to charging and discharging time. The scaling scheme of ILD and higher operation frequency for advanced processes will cause severe performance degradation due to unwanted parasitic capacitance. At the present stage of the development of the integrated circuit art, there is an increasing demand in the field of digital integrated circuits for faster switching circuits. With the switching demands of the integrated circuits going into higher frequencies, the slowing effect produced by parasitic capacitance becomes an increasing problem.